lsi l s3321 256 dot lcd micro-controller features : * 12 input/output pad. * direct drive buzzer output. * 3072x12 bit rom. * 176x4 bit of ram. * 32x4, x5, x6, x7 or 32x8 lcd segment. * 1/4 lcd bias. * 32768 crystal/rc oscillator bonding option. * single 1.5v operation. * low cost and low price. general description the LS3321 is a micro-controller for lcd applicatio n. it has an internal rom size of 3kx12bit. a 176x4 bit of ram, 32x4, x5, x6, x7 or x8 lcd seg ment with 1/4 bias. it has 12 i/o (mask option) pad. it directly drive a buzzer output. the buzze r driver can also be used as general purpose i/o by mask option. the system oscillator can be r/c or 3 2khz crystal oscillator. it is suitable for timer/calendar/controller function.
lsi LS3321 2 functional description 1. rc oscillator /crystal the LS3321 can use either a crystal oscilla tor or rc oscillator to provide the internal timing by bonding option. 2. program rom the LS3321 has internal 3kx12 bit rom providin g simple operation. it has six internal stacks. the program rom is page-segmented with 1k per page. to access pages higher than 1k, use the call instruction. the call instruction jumps to th e address defined by rompage.jjjjjjjjjj where jjjjjjjjjj is specified in the call instruction. 3. interrupt control the LS3321 has 5 different sources of interrup t, namely, powerup, f4hz, f16hza, f16hzs and f1hz. the starting address of the interrupt are as follow : interrupt address powerup 0x3ff f1hz 0x3fe f4hz 0x3fc f16hza 0x3f8 f16hzs 0x3f1 the system generates 16 interrupts for f16hzs in one second but only 11 interrupts for f16hza. the other 5 interrupts goes to f4hz (4) and f1hz (1 ) interrupts. 4. program ram the system has 128x4bit of program ram (00h to 7fh) with io address as follows. address description initialize 0h rptrl undefined 1h rptrh undefined 2h rptr1l undefined 3h rptr1h undefined 4h beep control 0 5h rom page 0 6h ram page 0 7h no use 0 8h iop0 io[0:3] 9h iop1 io[4:7] ah iop2 io[8:11] bh iop3 inp[0:3] ch(read) timer 1 value - ch(write) timer 1 data - dh(write) timer 1 control 0 fh(write) com/output (xxx0/xxx1) xxx0 10h-3fh system ram - 40h-7fh display ram - 80h-afh system ram -
lsi LS3321 3 address 1h:0h forms a 8bit address for indirect re ad/write operation for pointer read/write. address 3h:2h forms a 8bit address for indirect rea d/write operation for pointer1 read/write. indirect address is specified, for example, as ri nc #op indirect operand (#op) resulting address #0 rptrh.rptrl #1 rptrh.rptr1l #2 rptr1h.rptrl #3 rptr1h.rptr1l 5. buzzer control the system can output 4khz/2khz alarm signal b y mask option. the alarm signal is enabled to the output bd[0:1] when the beep control register: bit[ 0] is high. 6. timer/counter the 3321 has a 4 bit timer/counter. it is map to address ch and dh. address description ch(read) timer 1 value ch(write) timer 1 data dh(write) d3 1=start 0=stop no. use d1(tone) 1=fosc 0=phi12 d1(timer) 1=xinp0 0=f1hz d0 1=tone 0=buz
lsi LS3321 4 5. lcd driver the system has 32 lcd segment pad with 2-8 com mon pads (by mask option) providing 32x2,3,4,5,6,7,8 lcd segment output. the lcd segment table is shown below : common seg [1:32] 1 78h:d[0:3], 79h:d[0:3], 7ah:d[0:3], 7bh:d[0:3], 7ch:d[0:3], 7dh:d[0:3], 7eh:d[0:3], 7fh:d[0:3] 2 70h:d[0:3], 71h:d[0:3], 72h:d[0:3], 73h:d[0:3], 74h:d[0:3], 75h:d[0:3], 76h:d[0:3], 77h:d[0:3] 3 68h:d[0:3], 69h:d[0:3], 6ah:d[0:3], 6bh:d[0:3], 6ch:d[0:3], 6dh:d[0:3], 6eh:d[0:3], 6fh:d[0:3] 4 60h:d[0:3], 61h:d[0:3], 62h:d[0:3], 63h:d[0:3], 64h:d[0:3], 65h:d[0:3], 66h:d[0:3], 67h:d[0:3] 5 58h:d[0:3], 59h:d[0:3], 5ah:d[0:3], 5bh:d[0:3], 5ch:d[0:3], 5dh:d[0:3], 5eh:d[0:3], 5fh:d[0:3] or (masking option) 28h:d[0:3], 29h:d[0:3], 2ah:d[0:3], 2bh:d[0:3], 2ch:d[0:3], 2dh:d[0:3], 2eh:d[0:3], 2fh:d[0:3] 6 50h:d[0:3], 51h:d[0:3], 52h:d[0:3], 53h:d[0:3], 54h:d[0:3], 55h:d[0:3], 56h:d[0:3], 57h:d[0:3] 7 48h:d[0:3], 49h:d[0:3], 4ah:d[0:3], 4bh:d[0:3], 4ch:d[0:3], 4dh:d[0:3], 4eh:d[0:3], 4fh:d[0:3] 8 40h:d[0:3], 41h:d[0:3], 42h:d[0:3], 43h:d[0:3], 44h:d[0:3], 45h:d[0:3], 46h:d[0:3], 47h:d[0:3] 6. mask option name description bz2k/4k buzzer frequency bz[0], bz[1] buzzer control fsysprb power up control ina address description 0 watch dog reset 3 romh 5 romhh/oscon 4 off osc 5 on osc 6 off lcd 7 on lcd address description dh(write) d3 1=start 0=stop d2 1=xinp0 0=f1hz d1(tone) 1=fosc 0=fosc/2 d1(timer) 1=xinp0 0=f1hz d0 1=tone 0=buz
lsi LS3321 5 ? pin assignment designation type description b [0:1] output buzzer output v1, v2, vp1, vp2 output lcd bias vee output lcd power t2, t1 input (pl) test pin oo, ro output rc/32khz oscillator output oi input 32khz oscillator input vdd power +1.5v power supply gnd power ground i[0:11] i(ph)/o input/output pad pb reset low active c[1:8] output lcd common output s[1:32] output lcd segment output note: (pl) ? pull low (ph) - pull high
lsi LS3321 6 absolute maximum ratings supply voltage vdd - vss..........................0 to 5v input voltage vin.................................v ss to vdd operating temperature top .............-10 c to 60 c storing temperature tst ...................-40 c to 70 c *comments stress above those listed under } bsolute maximum ratings? may cause permanent d amage to the device. these are stress rating only. functional operati on of this device at these or any other conditions above those indicated in the operational sections of this spec ification is not implied and exposure to obsolute maximum rating conditions for extended periods may affect device reliability. d.c. electrical characteristics (gnd = 0v, vdd = 1.5v, ta = 25 c unless otherwise specified) parameter symbol min. typ. max. unit conditions supply voltage vdd 1.2 1.5 1.8 v operating current idd - 2 6 a no load osc. built-in cap cd - 20 - pf osc. trimmer cap ctrim 5 - 35 pf buzzer output current ib 500 - - a vbd-vss=0.5 lcd frequency flcd - 64 - hz segment current is 0.15 - - a vseg=0.2v common current ic 3.0 - - a vcom=0.2v
lsi LS3321 7 pad location pad x( ? m) y( ? m) pad x( ? m) y( ? m) s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32 1728.0 1604.0 1480.0 1356.0 1230.0 1030.0 902.0 702.0 574.0 374.0 246.0 46.0 -82.0 -282.0 -410.0 -610.0 -738.0 -938.0 -1066.0 -1266.0 -1394.0 -1594.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1368.0 -1370.0 -1240.0 -1110.0 -980.0 -850.0 -720.0 -590.0 -460.0 -330.0 -200.0 v2 v1 vp1 vp2 vee c1 c2 c3 c4 c5 c6 c7 c8 pb t1 t2 oo oi ro vdd b0 b1 gnd i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1830.0 -1662.0 -1532.0 -1402.0 -1272.0 -1142.0 -982.0 -355.0 +60.0 +194.0 +434.0 +820.0 +1058.0 +1188.0 +1318.0 +1448.0 +1578.0 +1728.0 +1728.0 +1728.0 +1728.0 +1728.0 +1728.0 +1728.0 +1728.0 -70.0 +60.0 +190.0 +320.0 +450.0 +580.0 +710.0 +840.0 +970.0 +1100.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1270.0 +1219.0 +1019.0 +885.0 +685.0 +551.0 +351.0 +217.0 +17.0
lsi LS3321 8 pad location
lsi LS3321 9 application circuit
|
